| Design Verification and Validation | Accelerate Verification, Streamline Challenges: A Comprehensive High Bandwidth Memory (HBM) Solution | Cadence Design Systems | SubashChandran; Dharini; Patel; Vatsal; Desai; Ritesh; Poshiya; Ujash |
| VLSI Design, Circuit and Architecture | Novel Circuit Techniques for High Speed Robust Two-Port SRAM | Samsung Semiconductor India R&D | Venkatasubramanian; Poorinma; Kumar; Lava; Sunanth Kumar; Gognieni Goopi; Suri; Puneet; Somashekara; Karthikeyan; Taigor; Subodh |
| VLSI Design, Circuit and Architecture | A Ripple-Based Adaptive On-Time Control Buck Converter With Pseudo Switch Node Ripple Injection | Samsung Semiconductor India R&D | Chittimreddy Jagannatham Reddy; Bhavitha; AV; Hareesh; Patra; Dr. Pradipta |
| Semiconductor Packaging, Integration, and System Design | Space Optimization in Thin Devices: Virtual Materials and Laser Direct Structuring (LDS) for Enhanced Antenna-Audio Integration and Radio Frequency Interference (RFI) Mitigation | Intel Corporation | Lingayat; Tejasweni; Gupta; Jay; Sudhakar; Shruthi; Subramanya; Bala; Thakur; Jayprakash; Pitchumani; Prasanna; Cherukatte; Sumod |
| AI Accelerators and Custom Hardware | A Survey of Noise-Resilient Quantum Aggregation Protocols for Federated Learning on NISQ Devices: NR-QFL and Applications in ADAS | PES University | K, Chethana; TS B; Dr. Sudarshan |
| Embedded Systems, Real-Time Computing, and Automotive Electronics | AI-Agent Driven Automated Firmware Code Generation in Embedded Systems | Intel Corporation | Aralguppe, Sowmya |
| VLSI Design, Circuit and Architecture | Modeling Cycle-Dependent uncertainty in multi-cycle latch paths | Nvidia | Panwalkar; Shweta; Suthar; Pratik; Kotha; Uhlas; Kansara; Hemal |
| VLSI Design, Circuit and Architecture | Low Power 2nm Ultra-Low Voltage SRAM Operating at 0.35V with Enhanced Read/Write Circuitry | Mediatek | K M, Aishwarya; Upadhye, Sanatkumar; Trivedi, Manish; Sidh; Jaswinder; Halli, Ramesh |
| Embedded Systems, Real-Time Computing, and Automotive Platforms | Virtualized GPIO framework for Multi VM Automotive Platforms | Samsung Semiconductor India R&D | Munawwara; Roshini; Aman, Ayush; Tailor, Devang |
| Communication, Connectivity, Multimedia, and Digital Twins | AAV-IRS-Based NOMA Wireless Communication System: Modeling and Performance Analysis | Birla Institute Of Technology And Science, Pilani | Choudhary; Neha; Joshi; Sandeep; Chaubey, Vinod Kumar |
| Design Verification and Validation | Optimizing Data Mismatch Debugging in Emulation-Based Subsystem Verification Using Offline FSDB based Checkers | Qualcomm | Immidisetti; Krishna Priyanka; Alphonse; Alvin; Sharma, Shubham; RK, Aravind |
| VLSI Design, Circuit and Architecture | Design of Capacitive-based MEMS Displacement Sensor using COMSOL | Central Manufacturing Technology Institute | N, Kusuma; KP, Chinmayi; G, Yashwanth |
| Communication, Connectivity, Multimedia, and Digital Twins | A Performance-Aware Framework for LDPC Code Enhancement Using Shortening Techniques | Samsung Semiconductor India R&D | Kamra; Bhawna; Srivastav; Ankit; Kamuganti; Vamshidhar; Angenei Ganapathi; Svarsha |
| AI Accelerators and Custom Hardware | Memory-Efficient GenAI Inference on Edge Devices Using Structured Weight sharing | Samsung Semiconductor India R&D | Pokuri; Madhavi; Prabhakar; Harsha |
| Communication, Connectivity, Multimedia, and Digital Twins | Handover Failure and Outage Prediction in 5G and Beyond UEs using Deep Learning | Samsung Semiconductor India R&D | BANSAL; NISHTHA; MISHRA; YOGESH KUMAR; POLASWAMY; ROHIT; SUNDARARAJAN; SATHIA CHANDRANE; BHARADWATKAM; SHRINATH RAMAMOORTHY |
| VLSI Design, Circuit and Architecture | Open-Source Emulation-based AI Framework for Performance & Verification in RISC-V SoCs | Samsung Semiconductor India R&D | Gorle; Pooja; Raju; Kumar; Kandyana, Dharani; M; Chinnadurai |
