Posters

Domain Title
AI/ML

Predicting SoC Lifespan with Prophet Algorithm

Mileni Trivedi, Bala Naveena, Afzal Hasan - Samsung

VLSI Verification

Debugging with Certainty: Harnessing Formal Verification for Debugging IP Sign-Offs

Rumia Masburah, Yuktha C, Venkatesh Chepuri, Ayush Sharma, Mahesh Shinde, Nitin Neralkar - Qualcomm

VLSI Verification

Self-Checking Mathematical Model for Efficient Verification of Distributed Tessellation Engines in Multi-Graphics Core Architecture

Aparna R Bhat, Ankita Gothi, Darshan Hurakadli, Shobhraj Singh, Sarang Kishor Mulay, Bholendra Pratap Singh, Anubhavkumar Shukla - Intel

VLSI Verification

Formal Verification of Image Processing Equivalence Beyond Complexity Bottleneck

Ketki Gosavi, Atharva Kakde, Pradeep Bagavathiappan, Anshul Singhal - Cadence Design Systems

VLSI Design & Implementation

Automating Schematic-Driven Layout Generation with Pin Creation and Placement to Optimize Workflows and Maximize Efficiency

Garima Batra, Neha Agrawal, Parv Malhotra, Hitesh Marwah - Cadence Design Systems

Automotive

Virtual Prototyping Solution for Software-in-the-Loop Validation

Anusha Upadhyaya, Hemalatha Mekala - Synopsys

Automotive

Accelerating ISO26262 Fault Campaign Closure Methodologies Augmented Through Automated Solutions

Paalini S, Mangesh Mukundrao Pande, Neha Jain, Anshul Singhal - Cadence Design Systems

Automotive

Statistically Accurate Analysis and Automated Measurement of Click and Pop Noise for Class-D Audio Amplifiers

Shruti Shukla, Arun Adoni, Pavinkumar Ramasamy, Ved Prakash, Sumit Dubey - Texas Instruments

Automotive

A Safe, Secure and Coherent Multi-Chip Architecture for ISO Compliant Automotive Solutions

Surekha C P, Shreya Joshi, Shrinidhi Rao, Bheema Thangavelu, Alok Kumar, Garima Srivastava - Samsung

Communications

AI-Enhanced Rule-Based Framework for Performance and Assertion Issue Analysis Across Multiple RATs

Rashika Manjini, Pooja Nayak, Amit Verma, Vikas Gupta, Parth Ashara, Jimmy-Yh Chen - MediaTek