Day 2

Data Drift Quantification Metrics for Month-on-Month Semiconductor Data.

Nandita Bhattacharya, Adrita Barari, Lakshmi Pedapudi, Hoyeon Kim, Kyuhwan Kim, Jihye Seo - Samsung

10:45 AM - 11:05 AM

Revolutionizing Workflow with AELU : Crafting a High-Precision, Time-Efficient Custom GPT Model.

Gunjan Rajput, Sanjiv Mathur - Cadence Design Systems

11:05 AM - 11:25 AM

Automated Camera Quality Calibration & Matching.

Sapna Kumari, Mintu Dutta, Adrita Barari, Jaeho Kwak, Yohwan Joo, Doyoung Kim - Samsung

11:25 AM - 11:45 AM

Domain Adaptation based Fin Height Measurement for DRAM.

Ramya Bagavath Singh, Gaurav Sultania, Lakshmi Narayana Pedapudi, Joonyoung Ahn, Je Ung Song, Hyomin Ahn - Samsung

11:45 AM - 12:05 PM

Novel Leakage Reduction Technique for Ultra Low Power Advanced FinFET Technology Node Design.

Sulagna Dey, Chaitanya Krishna, Srinivas Devalanka, Ravindra Ayyagari - AMD

10:45 AM - 11:05 AM

Simulation-Based Reliability Estimation of PCB Designs.

Gangireddy Sujatha - IIT, Delhi; Jasleen Kaur Ahuja, Taranjit Kukal - Cadence Design Systems; Shouri Chatterjee - IIT Delhi

11:05 AM - 11:25 AM

FPGA Based Adaptive Beamforming Using VSS LMS Algorithm.

Prabha G, Nidhiya Tittas - Amrita School of Engineering, Coimbatore

11:25 AM - 11:45 AM

Fabrication and Characterization of Directly Synthesized WSe2 Nano-flowers for NO2 Sensing.

Shikha Singh - IIT-BHU, Jogendra Singh Rana - SRM, AP, Satyabrata Jit - IIT BHU

11:45 AM - 12:05 PM

Resolving Care-bit Correlations using Clock Gates.

Shalini Pathak, Prateek Singh - STMicroelectronics Ltd., Sandeep Jain - Siemens

10:45 AM - 11:05 AM

Cell-Aware ATPG under Electrical Voltage Stress.

Shruthi Shekarappa, Swetha Priya Aenikapati, Navdeep Sood, Nand Kishore, Sahil Narang, Sameer C Chillarige - Cadence Design Systems

11:05 AM - 11:25 AM

An efficient Scandump methodology to left shift DFT testing into Gate-level Verification.

Kavya R, Shrinidhi Rao, Sanjoy Saha, Alok Kumar, Seonil Brian Choi, Garima Srivastava - Samsung

11:25 AM - 11:45 AM

Optimization and Debug of FIVR Parameters in Server SoC Power Delivery Network: A Post Silicon Approach with On-Die DFx

Susan Vinoth, Vijayaanandh J P, Uday Bhaskar Kadali - Intel

11:45 AM - 12:05 PM

SEASR : Speech Enhancement for Automatic Speech Recognition Systems using Convolution Recurrent Neural Network with Residual Connections.

Manasi Remane, Revanth Reddy Nalla, Ambrish Dantrey - NVIDIA

12:15 PM - 12:35 PM

Fairness in Reconfigurable Intelligent Surface (RIS) assisted MU-MISO systems Using DRL.

Arpita Thakre, SRIVATSA DASA L - PES University

12:35 PM - 12:55 PM

Enhanced Seamless Multi-Device Experience Across Different Ecosystems.

Rajini kumari bevara, siva Nageswara Rao Bandreddy, vimal singh, Nikhil Kansal - Qualcomm

12:55 PM - 1:15 PM

Exploratory Approach to reduce IR issue in Low Power Test Compression Methodology.

Swetha Priya Aenikapati, Ashwini Shankar, Manju Bhargavi Jella - Cadence Design Systems

12:15 PM - 12:30 PM

Post-Silicon DV : Simplifying and Accelerating a Complex Debug Journey.

Ankita Mohanty, Risita Jena, Prashanth Saraf, Sidhartha Kumar, Ashwini Padoor, Desmond Fernandes - Texas Instruments

12:30 PM - 12:45 PM

Interoperable SoC Framework for PCIe design verification challenges.

Nirupama K G, Narasimhababu GVL - Synopysys

1:00 PM - 1:15 PM

SDV-Aware Evolved Automotive Safety Architecture.

Neha Srivastava- NXP

12:15 PM - 12:35 PM

Design and Implementation of a Decentralized Voting System Using Volta Blockchain.

Arthi Murugadass, Rohit Bharadwaj, Avrit M, Gogineni Jaswant, Siranjeevi GP - VIT, Chennai, SUGANTHI EVANGELINE - Sri Eshwar College of Engineering

12:35 PM - 12:55 PM

Breakthrough Hardware Solutions for Post-Quantum Security with QC-MDPC Codes.

Mehar Latif - Intel

12:55 PM - 1:15 PM